Time and Area Optimization in Processor Architecture

For specified program behavior and clocking overhead, there is an optimum cycle time. This can be improved somewhat by using wave pipelining, but program unpredictability ultimately limits performance by restricting both cycle time and instruction level parallelism. Algorithm and application implementation should be based on understanding of program behavior, CAD tools, and technology. System on a chip can be realized as die potential increases. This system die then consists of collecting a variety of functional implementations and chip. These include core processor, floating point unit signal processors, cache, message compression and encryption, etc. Functional implementations involve selecting particular algorithms so that total application execution time is minimized under the constraints of fixed die area. Underlying all improvements in processor architecture are fundamental notions of the optimum use of time and space. In silicon CMOS technologies, the notion of optimum cost– performance is translated into performance–area optimality, as chip area largely determines chip cost (with the other major determinant being manufacturing volume). In the process of optimizing time and space, we deal with a complex set of tradeoffs involving a number of technology sub-disciplines. Time optimization requires control over VLSI fab processing, state of the art CAD tools and an understanding of physical constraints such as power and heat dissipation. An understanding of algorithms allows the user to select the best design choices within area–time restrictions. Selecting good algorithms also requires a broad understanding of available technology, behavior of user applications, and available software [4]. Finally, there is die area itself. This is a primary determinant of marginal production cost. In an era of increasing availability of chip area through improved technology (reduced feature size), the issue becomes one of selecting functions that make optimum use of marginally available area. Table 1 shows the projected performance area improvement for silicon die over the next ten years. Silicon die that in 1997 have 10 million transistors will be replaced in ten years by die that have more than 25 times that number of active devices. Cycle time is also on a similar curve, so that gigahertz or subgigahertz cycle times are expected in the same time frame. This work has been supported in part by the National Science Foundation under grant MIP-9313701.